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HV6810 10-Channel Serial-Input Latched Display Driver
Features
High output voltage 80V High speed 5MHz @ 5.0VDD Low power IBB 0.1mA (all high) Active pull down 100A min Output source current 100mA at 60V VPP Each device drives 10 lines High-speed serially-shifted data input 5.0V CMOS-compatible inputs Latches on all driver outputs Pin-compatible replacement for UCN5810A and TL4810A, TL4810B
General Description
The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high, and is latched when the latch enable is low. When the blanking input is high, all of the outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80V and 25mA source-current capability. All inputs are compatible with CMOS levels.
Applications
High speed dot matrix print head driver VFD (vacuum fluorescent display) driver
Ordering Information
Device HV6810 Package Options 20-J Lead PLCC HV6810PJ-G 20-Lead SOW HV6810WG-G
Pin Configurations
1 20
20
-G indicates package is RoHS compliant (`Green')
1
20-J Lead PLCC (PJ)
(top view)
20-Lead SOW (WG)
(top view)
Absolute Maximum Ratings
Parameter Logic supply voltage, VDD(1) Driver supply voltage, VBB Output voltage(1) Input voltage(1) Continuous total power dissipation at 25OC free-air temperature 20-J Lead PLCC (PJ) 20-Lead SOW (WG) Operating temperature range
(1)
Value 7.5V 90V 90V -0.3V to VDD+ 0.3V
Product Marking
Top Marking
YY = Year Sealed WW = Week Sealed L = Lot Number Bottom Marking C = Country of Origin* A = Assembler ID* = "Green" Packaging CCCCCCCCCCC
YYWW
HV6 8 1 0 PJ
LLLLLLLLLL
AAA
*May be part of top marking
20-J Lead PLCC (PJ) 1000mW(2) 1000mW(2) -45C +85C
Top Marking
YYWW
HV6810WG
LLLLLLLLLL
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: (1) All voltages are referenced to VSS. (2) For operation above 25OC ambient derate linearly to 85OC at 16.7mW/OC.
Bottom Marking
CCCCCCCCCCC AAA
YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging
*May be part of top marking
20-Lead SOW (WG)
HV6810
Recommended Operating Conditions
Sym VDD VBB VSS VIH VIL IOH fCLK TA Parameter Supply voltage Supply voltage Supply voltage High-level input voltage (for VDD = 5.0V) Low-level input voltage Continuous high-level Q output current Clock frequency Operating ambient temperature Min 4.5 20 3.5 -0.3 -25 -40 Typ 0 Max 5.5 80 5.3 0.8 5.0 +85 Units V V V V V mA MHz C Conditions -----------------
Power-Up / Power-Down Sequence
Step 1 2 3 4 5 Description Connect ground VSS Apply VDD Set all inputs (Data, CLK, Enable, etc.) to a known state Apply VBB The VBB should not drop below VDD or float during operation.
Power-down sequence should be the reverse of the above.
DC Electrical Characteristics
(VDD = 5V10%, VBB = 60V, VSS = 0, TA = 25OC unless otherwise noted)
Sym VOH
Parameter High level output voltage Q outputs Serial output Q outputs Serial output
Min 57.5 4.0 60 -
Typ 58 4.5 0.15 0.05 80 -1.0
Max 1.0 0.1 -15 1.0
Units V
Conditions IOH = 25mA VDD = 4.5V, IOL = -100A IOH = 100A, blanking input at VDD VDD = 4.5V, IOL = 100A TA = Max, VOL = 0.7V VO = 0, Blanking input TA = Max at VDD Vl = VDD All inputs at 0V, one Q output high All inputs at 0V, all Q outputs low All outputs low, all Q outputs open All outputs high, all Q outputs open
VOL IOL IO(OFF) IH IDD
Low level output voltage
V A A A
Low level Q output current (pull-down current) Off-state output current High level input current
10 10 0.05 0.05
50 A 50 0.1 mA 0.1
Supply current from VDD (standby) -
IBB
Supply current from VBB -
* All typical values are at TA = 25OC except for IO.
2
HV6810
AC Electrical Characteristics
(Timing requirements over recommended operating conditions)
Sym tW(CKH) tW(LEH) tSU(D) tH(D) tCKH-LEH tPD
*
Parameter Pulse duration, clock high Pulse duration, latch enable high Setup time, data before clock Hold time, data after clock Delay time, clock to latch enable high Propagation delay time, latch enable to output
Min 100 100 50 50 50 -
Typ 0.3
Max -
Units ns ns ns ns ns ns
Conditions -------------
* Switching characteristics, VBB = 60V, TA = 25OC
Switching Waveforms
t w(CKH) V IH Clock 50% 50% V IL t su(D) Valid Data 50% 50% V t h(D) V IH Output Clock Input 50% Valid t CKH-LEH Latch Enable 50% t pd 90% Valid t w(LEH) 50% V IH V IL V IH V IL
Input Timing
Output Switching Times
Timing Diagram
Clock
Data In
VALID
IRRELEVANT
SR Contents
INVALID
VALID
Latch Enable
Latch Contents
PREVIOUSLY STORED DATA
NEW DATA VALID
Blanking
Q Outputs
VALID
3
HV6810
Input and Output Equivalent Circuits
VDD VBB
Input
Output
VSS Input Equivalent Circuit Logic Data Output
VSS
Functional Block Diagram
Logic Diagram (positive logic)
Blanking Latch Enable Shift Register Data Input Clock 1D C1 R1 Latches C2 2D LC1 Q1
1D C1
R2
C2 2D
LC2
Q2 6 Stages (Q3 thru Q8) not shown Q9
* * *
* * * 1D C1 R9
* * * C2 2D LC9
* * *
1D C1
R10
C2 2D
LC10
Q10 Serial Out
Function Table
Serial Data Input H L X Clock Input Shift Register Contents I1 I2 I3 ... IN-1 IN H R1 R2 ... RN-2 RN-1 L R1 R2 ... RN-2 RN-1 R1 R2 R3 ... RN-1 RN X X X ... X ----X Serial Data Output RN-1 RN-1 RN X PN --L H --R1 R2 R3 ... RN-1 RN P1 P2 P3 ... PN-1 PN X X X ... X X L H P1 P2 P3 ... PN-1 PN L L L ... L L --------Strobe Input Latch Contents I1 I2 I3 ... IN-1 IN Blanking Input Output Contents I1 I2 I3 ... IN-1 IN
P1 P2 P3 ... PN-1 PN ---
4
HV6810
Pin Descriptions
HV6810 20-J Lead PLCC (PJ)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Q8 Q7 Q6 CLOCK N/C VSS VDD LE (STROBE) Q5 Q4 Q3 Q2 Q1 BLANKING DATA IN N/C VBB SERIAL DATA OUT Q10 Q9 When blanking is low, all Q's are forced to a high state, regardless of data in each channel. When OL is low, all Q's are forced to a low state, regardless of data in each channel. Input data for the input shift register. No connection. High voltage power supply. Output data from the shift register. High voltage output. High voltage output. Input data are shifted into the data shift register on the thepostive edge of the clock. No connection. Usually VSS = 0, ground connection. Low voltage power supply. When LE is high, data is transferred from data shift register to the Q output latch. When LE is low, data is latched into data latches and new data can be clocked into the shift register. High voltage output. Description
5
HV6810
Pin Descriptions
HV6810 20-Lead SOW (WG)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Q8 Q7 Q6 CLOCK VSS N/C VDD LE (STROBE) Q5 Q4 Q3 Q2 Q1 BLANKING DATA IN VBB SERIAL DATA OUT N/C Q10 Q9 When blanking is low, all Q's are forced to a high state, regardless of data in each channel. When OL is low, all Q's are forced to a low state, regardless of data in each channel. Input data for the input shift register. High voltage power supply. Output data from the shift register. No connection. High voltage output. High voltage output. Input data are shifted into the data shift register on the thepostive edge of the clock. Usually VSS = 0, ground connection. No connection. Low voltage power supply. When LE is high, data is transferred from data shift register to the Q output latch. When LE is low, data is latched into data latches and new data can be clocked into the shift register High voltage output.
6
HV6810 20-J Lead PLCC Package Outline (PJ)
.353x.353in body, .180in height (max.), .050in pitch
.048/.042 x 45O 3 D D1 1 .056/.042 x 45O
20
.150 MAX Note 1 (Index Area) .075 MAX E1 E 18
8
.020 MAX 3 Places
13
Top View
View B b1 A A1 A2 e Base Plane .020 MIN Seating Plane b
Side View
View B
Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (inches) NOM MAX
A .165 .172 .180
A1 .090 .105 .120
A2 .062 .083
b .013 .021
b1 .026 .032
D .385 .390 .395
D1 .350 .353 .356
E .385 .390 .395
E1 .350 .353 .356
e .050 BSC
JEDEC Registration MS-018, Variation AA, Issue A, June, 1993. Drawings not to scale.
7
HV6810 20-Lead SOW (Wide Body) Package Outline (WG)
12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch
D
20 1
E1
Note 1 (Index Area 0.25D x 0.75E1) 1
E
L2
Gauge Plane
L L1
Seating Plane
Top View
A
View B
View B
h A A2 e
Seating Plane
h
Note 1
A1
b A
Side View
View A-A
Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension NOM (mm) MAX
A 2.15 2.65
A1 0.10 0.30
A2 2.05 2.55
b 0.31 0.51
D 12.60 12.80 13.00
E 9.97 10.30 10.63
E1 7.40 7.50 7.60
e 1.27 BSC
h 0.25 0.75
L 0.40 1.27
L1 1.40 REF
L2 0.25 BSC
0 8
O
1 5O 15O
O
JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. Drawings not to scale.
(The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV6810 A101507
8

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